The present invention relates generally to a semiconductor memory device, and more particularly to a mask ROM including a memory transistor to which data is fixedly written as a difference between threshold voltages depending on an existence and non-existence of a doped channel layer.
A mask ROM in which data are fixedly stored by mask programing has hitherto been known as a read-only semiconductor memory. The mask ROM may be functionally structured so that an indication of whether or not the memory transistor is disposed at an intersection between a bit line and a word line is set corresponding to data "1" or "0". A diffused layer program mode shown in FIG. 19 and a contact program mode shown in FIG. 20 have been used as a programing mode of the mask ROM having a comparatively small memory capacity.
A mask ROM in which data are fixedly stored by mask programming has hitherto been known as a read-only semiconductor memory. The mask ROM may be functionally structured so that an indication of whether or not the memory transistor is disposed at an intersection between a bit line and a word line is set corresponding to data "1" or "0". A diffused layer program mode shown in FIG. 19 and a contact program mode shown in FIG. 20 have been used as a programming mode of the mask ROM having a comparatively small memory capacity.
Referring to FIGS. 19 and 20, a region indicated by hatching is a device isolation region, and a memory transistor MC corresponds to an intersection between a word line WL and a bit line BL. According to the diffused layer program mode in FIG. 19, the data is written depending on whether a diffused layer is formed at the area of the memory transistor which is surrounded by a broken line. According to the contact program mode in FIG. 20, the data is written depending on whether or not a bit line contact of the memory transistor MC surrounded by a broken line is formed. Both cases take a NOR type cell structure in terms of an equivalent circuit as shown in FIG. 21.
In the diffused layer program mode, though capable of enhancing integration, the diffused layer is formed at an initial stage of a process of manufacturing the memory, and hence a TAT (Turn Around Time) elongates. The contact program mode, because of being a program after forming the device, has a shorter TAT than in the diffused layer program mode but less integration.
By contrast, a NAND type cell shown in FIGS. 22 and 23 is used as the mask ROM capable of enhancing the integration. A region indicated by hatching in FIG. 22 is a device isolation region, wherein the memory transistors are connected in series to the bit line. The programming is executed depending on whether channel ion implantation is performed beforehand into a memory transistor MC region defined by a broken line. For example, the memory transistor formed with a doped channel layer is categorized as a depletion (D) type, the memory transistors other than the D-type are classified as an enhancement (E) type. It follows,
as shown in FIG. 23, that the data is written as a distribution of the E- and D-types.
A cell structure of the large-capacity mask ROM includes a contactless type cell shown in FIG. 24 in addition to the NAND type cell. The contactless type cell is obtained by providing n.sup.+ type diffused layers in strips on the semiconductor substrate, thereafter providing a gate oxide layer over the entire surface, and pattern-forming word lines WL thereon by using polysilicon layers. Three strips of adjacent n.sup.+ type diffused layers become, as illustrated in FIG. 24, a bit line BL and ground lines VSSO, VSSl between which the bit line BL is interposed. All the regions just under the word lines interposed between the n.sup.+ type diffused layers serve as channel regions of the memory transistors. The data is written depending on whether ion implantation into the channel region of one single memory transistor indicated by the broken line is performed or not.
There were, however, limits to the high integrations of the mask ROMs of the NAND type cell and of the contactless type cell. A major factor therefor is that the channel ion implantation of the memory transistor might involve a deviation in mask alignment, and hence a design rule for the channel ion implantation must have some allowance. Therefore, if the memory transistor is downsized, a lower limit of a memory cell size is resultantly specified by the design rule for the channel ion implantation, and a further downsized structure is hard to obtain.